Analog Layout Engineer
Meta

Job Info

Join Meta's Wearable Silicon AMS team as an Analog Layout Engineer and play a key role in developing cutting-edge AMS IP's that enable the next generation of virtual and augmented reality systems. As an Analog IC Layout Engineer, you will work with a world-class group of engineers creating high performance and area/power efficient custom layouts in advanced CMOS process nodes for our next generation AR/VR products. You will work closely with circuit designers and the physical design team to define the IC floor-plan, chip partitioning and power distribution.

Analog Layout Engineer Responsibilities:

• Design and optimize complex layouts for mixed signal and analog circuits in deep sub-micron CMOS technologies
• Collaborate with circuit designers to floor plan and complete layouts, ensuring seamless integration and optimal performance
• Run physical design/reliability verification, debug and fix violations, ensuring the highest quality and reliability of our AMS IP's
• Review and analyze layouts with circuit designers, providing expert feedback and guidance to ensure optimal design
• Contribute to layout integration and final verification for tape out, ensuring a smooth and successful project delivery

Minimum Qualifications:

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
• Bachelor's degree in Electrical Engineering, or relevant technical field, or equivalent practical experience
• 3+ years of experience as an IC Layout Designer with analog/mixed signal layout experience
• Proven experience with layout techniques for device matching, noise isolation, electro-migration, power distribution, latch-up and ESD circuits using state of the art nanometer process technologies
• Proficiency with Cadence Virtuoso XL layout tool and Mentor Calibre physical design verification tools (DRC, LVS, ERC) or equivalent
• Experience debugging and resolve LVS/DRC/ERC errors independently

Preferred Qualifications:

• Exposure to FinFET process technology and its constraints for analog layout techniques and qualities
• Familiarity with Cadence Virtuoso advanced features, such as schematic and constraint driven layout, auto routing
• Experience with Place and Route tools and scripting languages (perl, TCL, Python, or Cadence Skill)
• Experience with memory layout

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